Donetsk National Technical University
Please use this identifier to cite or link to this item:
https://ea.donntu.edu.ua/jspui/handle/123456789/2860| Title: | Уменьшение аппаратурных затрат в схеме МПА Мура при реализации на CPLD |
| Authors: | Баркалов, А.А. Цололо, С.А. |
| Keywords: | PAL CPLD макроячейка МПА Мура уменьшение аппаратурные затраты |
| Issue Date: | 2008 |
| Series/Report no.: | Научные труды ДонНТУ. Серия "Вычислительная техника и автоматизация". Выпуск 15 (130), 2008; |
| Abstract: | Method of Moore’s circuit optimization is proposed. The method is based on use of free outputs EMB blocks for representation the codes of classes of pseudoequivalent states. The proposed approach allows to reduce number of PAL macrocells in Moore FSM without decrease of digital system performance. The carried out researches have shown that the method reduces hardware expenses up to 28%. |
| URI: | http://ea.donntu.edu.ua/handle/123456789/2860 |
| Appears in Collections: | Наукові публікації кафедри комп'ютерної інженерії |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| 2008, 12 (Donetsk, VTA).pdf | 8,97 MB | Adobe PDF | View/Open |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.