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Title: Reduction of hardware amount for control unit with address transformer
Authors: Barkalov, Alexandr A.
Titarenko, Larisa A.
Lavrik, Alexandr S.
Keywords: CPLD
Issue Date: 8-Jan-2012
Abstract: The method of hardware reduction is proposed oriented on control units and CPLD chips. The method is based on a wide fan-in of PAL macrocells allowing using more than one source of microinstruction address. The method of logical condition replacement is used for optimization of microinstruction addressing block. An example of proposed method application is given.
Appears in Collections:Наукові публікації кафедри комп'ютерної інженерії

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