Please use this identifier to cite or link to this item:
https://ea.donntu.edu.ua/jspui/handle/123456789/3707Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Barkalov, Alexandr A. | - |
| dc.contributor.author | Titarenko, Larisa A. | - |
| dc.contributor.author | Lavrik, Alexandr S. | - |
| dc.date.accessioned | 2012-01-08T12:09:37Z | - |
| dc.date.available | 2012-01-08T12:09:37Z | - |
| dc.date.issued | 2012-01-08 | - |
| dc.identifier.uri | http://ea.donntu.edu.ua/handle/123456789/3707 | - |
| dc.description.abstract | The method of hardware reduction is proposed oriented on control units and CPLD chips. The method is based on a wide fan-in of PAL macrocells allowing using more than one source of microinstruction address. The method of logical condition replacement is used for optimization of microinstruction addressing block. An example of proposed method application is given. | en_US |
| dc.language.iso | en | en_US |
| dc.subject | CPLD | en_US |
| dc.subject | PAL | en_US |
| dc.subject | CMCU | en_US |
| dc.title | Reduction of hardware amount for control unit with address transformer | en_US |
| dc.type | Article | en_US |
| Appears in Collections: | Наукові публікації кафедри комп'ютерної інженерії | |
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