Donetsk National Technical University
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https://ea.donntu.edu.ua/jspui/handle/123456789/8685| Title: | Hardware methods to increase of algorithms for distributed logic simulation |
| Authors: | Ладыженский Ю.В. Тесленко Г.А. |
| Keywords: | distributed logic simualtion hardware acceleration |
| Issue Date: | May-2006 |
| Publisher: | Харьковский национальный университет радиоэлектроники |
| Citation: | Ladyzhensky Y.V., Teslenko G.A. Hardware methods to increase of algorithms for distributed logic simulation. // Proceeding of IEEE East-West Design & Test Workshop (EWDTW’06). Sochi, September 15-19, 2006. 484p. –pp.385 |
| Abstract: | The subject of research is methods of hardware implementation of synchronization algorithms for a distributed logical simulation. The main idea is a creation of a structural model from a set of functional units. This provides equivalent mapping algorithms for a computational processes and data processing operations. |
| URI: | http://ea.donntu.edu.ua/handle/123456789/8685 |
| Appears in Collections: | Публікації у збірниках праць конференцій |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| EWDTW'06_Teslenko Sochi 2006.pdf | 70,64 kB | Adobe PDF | View/Open |
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