Reducing the number of PAL macrocells in Moore FSM

Abstract

A method of Moore’s circuit optimization is proposed. The method is based on the features of CPLD architecture and Moore’s FSM model. The example of the offered method is given. The carried out researches have shown that the method reduces hardware expenses up to 30%. The scien- tific novelty of the proposed method is reduced to usage of peculiarities of both the Moore FSM

(the existence of pseudoequivalent states) and CPLD (the wide fan-in of PAL macrocells). These peculiarities are used for decreasing the number of PAL macrocells in the Moore FSM’s logic circuit. The practical meaning of the proposed method is determined by the diminishing the area of SoC occupied by the logic circuit of a control unit in comparison with known approaches.