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dc.contributor.authorIvanov, Dmitry-
dc.contributor.authorSkobtsov, Yurij-
dc.contributor.authorEl-Khatib-
dc.date.accessioned2011-10-12T07:08:26Z-
dc.date.available2011-10-12T07:08:26Z-
dc.date.issued2006-
dc.identifier.citationSkobtsov Y.A., El-Khatib, Ivanov D.E. Distributed Fault Simulation and Genetic Test Generation of Digital Circuits // Proceedings of IEEE East-West Design&Test Workshop (EWDT’06).- 2006: Sochi.- p.89-94.en_US
dc.identifier.urihttp://ea.donntu.edu.ua/handle/123456789/1450-
dc.description.abstractFault simulation is on of the most highly compute-intensive task in the technical diagnostics. One of the ways to speed-up this process is a parallelization on the calculation cluster. In this paper a distributed algorithm for fault simulation of digital circuits is presented. It is based on the well-known «master-slave» approach in which one processor is nominating as a master and rules all calculation on the all slave’s processors. To reach the maximal utilization of the processors in the cluster it is used schema with static fault list partitioning.en_US
dc.language.isoenen_US
dc.publisherProceedings of IEEE East-West Design&Test Workshop (EWDT’06).en_US
dc.subjectdigital circuiten_US
dc.subjectgenetic algorithmen_US
dc.subjectfault simulationen_US
dc.subjectparallel simulationen_US
dc.subjectmulti-core processoen_US
dc.subjectislands modelen_US
dc.titleDistributed Fault Simulation and Genetic Test Generation of Digital Circuitsen_US
dc.typeArticleen_US
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