Please use this identifier to cite or link to this item: http://ea.donntu.edu.ua:8080/jspui/handle/123456789/1443
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dc.contributor.authorИванов, Дмитрий Евгениевич-
dc.date.accessioned2011-10-12T06:44:28Z-
dc.date.available2011-10-12T06:44:28Z-
dc.date.issued2009-
dc.identifier.citationD.E. Ivanov Parallel fault simulation on multi-core processors // «Радіоелектронні і комп’ютерні системи», 2009.- №6(40).- С.109-112. (Четвёртая международная научно-техническая конференция «Гарантоспособные» (надёжные и безопасные) системы, сервисы и технологии, Украина, Кировоград, 22-25 апреля, 2009)en_US
dc.identifier.urihttp://ea.donntu.edu.ua/handle/123456789/1443-
dc.description.abstractIn this paper we propose a fault simulation algorithm that utilizes all cores in multi-core processors. We adapt for multi-core workstation our early proposed distributed fault simulation algorithm. Proposed algorithm uses multi thread execution. The algorithm is based on the well-known «master-slave» approach in which one thread is nominated as a master and controls the calculation on all the other cores of processor. To maximize utilization of the cores a scheme with static fault list partitioning is used. The speed-up coefficient of the simulation time obtained during machine experiments is up to 3.44 times on the quad core system.en_US
dc.publisher«Радіоелектронні і комп’ютерні системи»en_US
dc.subjectdigital circuiten_US
dc.subjectsequential circuiten_US
dc.subjectfault simulationen_US
dc.subjectparallel simulationen_US
dc.subjectmulti-core processoen_US
dc.subjectexecution threaden_US
dc.titleParallel fault simulation on multi-core processorsen_US
dc.typeArticleen_US
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