OPTIMIZATION OF MICROPROGRAM CONTROL UNIT BASED ON CPLD FEATURES

Abstract

The method of hardware reduction is proposed which is oriented on compositional micro-program control units and PAL-based CPLD chips. The method is based on a wide fan-in of PAL macrocells allowing using more than one source of microinstruction address. Such ap-proach permits to minimize the number of PAL macrocells used for transformation of micro-instruction address. Conditions for this method’ application and example of its application are given. The results of experiments are shown.