Please use this identifier to cite or link to this item: http://ea.donntu.edu.ua:8080/jspui/handle/123456789/22606
Title: ОПТИМИЗАЦИЯ СХЕМЫ АДРЕСАЦИИ КМУУ С ЭЛЕМЕНТАРНЫМИ ЦЕПЯМИ
Other Titles: Optimization of Addressing Circuit for CMCU with Elementary Chains
Оптимізація схеми адресації КМПК із елементарними ланцюгами
Authors: Баркалов, А.А.
Ефименко, К.Н.
Зеленева, И.Я.
Barkalov, A.A.
Yefimenko, K.N.
Zelenjova, I.J.
Баркалов, О.О.
Єфіменко, К.М.
Зеленьова, I.Я.
Keywords: композиційний мікропрограмний пристрій керування
ГСА
елементарний операторній лінійний ланцюг
FPGA
логічна схема
compositional microprogram control units
GSA
elementary operational linear chains
logic circuit
КМУУ
ЭОЛЦ
логическая схема
Issue Date: 2013
Publisher: Донецький національний технічний університет
Citation: Наукові праці Донецького національного технічного університету. Серія: Обчислювальна техніка та автоматизація. Випуск 1 (24). - Донецьк, ДонНТУ, 2013. С - 214-221
Abstract: Предлагается метод уменьшения аппаратурных затрат в схеме КМУУ с элементарными цепями, ориентированный на технологию FPGA. Метод основан на использовании трех ис- точников кодов классов псевдоэквивалентных ЭОЛЦ и мультиплексора, позволяющего вы- брать один из этих источников. Такой подход позволит уменьшить число LUT элементов в схеме адресации КМУУ. Приведен пример применения предложенного метода.
Description: The article is devoted to the development of synthesis and optimization methods of compositional microprogram control units (CMCU) on FPGA (field-programmable logic arrays). Compositional microprogram control unit, particularly the structure of CMCU with code sharing, is effective tool for application of linear control algorithm. For optimization of a system-on-a-chip resources, applied in realization of the compositional microprogram control unit, the method of a structural reduction is used. A method for reducing the hardware amount in the circuit of CMCU with elementary chains oriented on FPGA technology is proposed. This method is based on the usage of three sources of codes classes of pseudoequivalent EOLC (elementary operational linear chains) and a multiplexer to choose one of these sources. Main steps of proposed method include: forming and optimal encoding of EOLC; definition of classes of pseudoequivalency; transforming of tne initial table of transitions and sharing it by two parts according to the classes; forming of control memory content; definition of functional expressions for the block of code transforming. Such an approach would reduce the number of LUT (look-up table)-elements in the addressing circuit of CMCU. Application of the specified method to the finite state machine of addressing CMCU, under its implementation with FPGA, leads to reduction of the number of LUT-elements in the circuit of the control unit. Moreover, modern FPGA contains macrocells of embedded memory blocks (EMB). Such blocks can be reconfigured towards changing of input’s and output’s number with saving of fixed square of EMB macrocell. This property allows to apply the combinational circuit for multiplexer of code source using the tristable outputs of EMB. Proposed method uses this property for reducing the number of used macrocells in the logic circuit of CMCU. Results of research of the developed structures, allowing defining their efficiency and an area of optimum application, are discussed. And the example of the application of proposed method is given.
URI: http://ea.donntu.edu.ua/handle/123456789/22606
ISSN: 2075-4272
Appears in Collections:Випуск 1 (24)'2013

Files in This Item:
File Description SizeFormat 
баркалов.pdf432,89 kBAdobe PDFView/Open


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.